1. Field of the Invention
The present invention relates generally to the field of analog-to-digital converters (ADCs) and more particularly, to Sigma-Delta ADCs with reduced jitter sensitivity and power consumption.
2. Description of the Prior Art
With the advent of the digital age, technology has rapidly advanced in the recent decades. One of the results of this growth is faster digital products and with greater accuracy. As digital circuits require higher accuracy, resolution requirements need be increased. Analog-to-digital converters (ADCs), which convert an analog signals to digital form similarly have requirements for higher resolution because they need to keep up with the requirements of digital circuits, as they provide the digital signals employed by their corresponding digital circuits.
Some ADC designs use various operational amplifier circuits with each amplifier circuit comprising a stage of the ADC. Sigma-delta type of ADCs are commonly employed by the industry and at every stage, they typically use an operational amplifier circuit.
The operational amplifier circuit includes an operational amplifier with a feedback path. The feedback path typically comprises an integration capacitor coupled between the output of the amplifier and an input of the amplifier with a remaining input of the amplifier being coupled to an alternating current (AC) ground. To this end, there are two known ways of implementing Sigma-Delta ADCs. One is using continuous-time (CT) feedback approach and another is using discrete-time feedback (or switched-capacitor (SC) feedback) approach.
The CT feedback approach generally uses a current source coupled to the input of the amplifier to which the integration capacitor is coupled, essentially serving to integrate the charge onto the integration capacitor for a corresponding stage. The current source provides a constant current level across the integration capacitor when the integration capacitor is being charged and when integration stops, undesirably, jitter results. An input voltage, Vi, is provided as input to the stage of the ADC and a resistor is used to translate the input voltage to current that essentially integrates on the integration capacitor. The distinguishing feature between the CT feedback and the SC feedback approaches is the feedback path in that the former, feedback is continuous in time and in the latter, feedback is discontinuous or switched.
The feedback factor, QFB, in the continuous-time case is determined by the total charge integrated:
                              Q          FB                =                                            I              FB                        ⁢            T                    2                                    Eq        .                                  ⁢                  (          1          )                    where IFB is the current generated by the feedback current source and T/2 represents integration time used for integrating the feedback signal as well as the in-coming analog signal.
A plot of the feedback charge, QFB, versus time, t, is shown in FIG. 1. FIG. 1 shows a graph of current versus time and the integration of the IFB pursuant to a continuous-time (CT) Sigma-Delta feedback technique used a prior art ADC design.
As shown in FIG. 1, at approximately the time, T/2, or integration cycle, the feedback signal faces some uncertainty due to jitter or uncertainty in the clock edge.
Therefore, the CT design approach, while being fairly low in its power consumption, suffers from being extremely sensitive to clock jitter. Jitter results from uncertainty at the end of the integration (or sampling) time due to the uncertainty in the clock edge. This is shown in FIG. 1 and represented by the following equation:ΔQFB=IFBtj  Eq. (2)
Where tj represents variation (or change) at then integration stop time (or the end of the integration time) and ΔQFB is the corresponding change in the feedback charge. The corresponding input-referred noise of the stage is shown in the following equation:
                              v          ninp                =                                            Δ              ⁢                                                          ⁢                              Q                FB                                                                    R                in                            ⁢              T                                =                                                    I                FB                            ⁢                              t                j                                                                    R                in                            ⁢              T                                                          Eq        .                                  ⁢                  (                      2            ⁢                          -                        ⁢            a                    )                    
In the graph of FIG. 1, the y-axis represents current across the integration capacitor and the x-axis represents time. The current rises up to IFB during a time duration of T/2, however on or about time T/2 when integration cycle ends, the time jitter effect undesirably causes sampling inaccuracy. Stated differently, the change in QFB causes an undesirable jitter time effect. In lower-end ADCs jitter sensitivity may be acceptable, however, higher resolution ADCs cannot tolerate such sensitivity.
In the case of the SC feedback, a feedback capacitor is employed in place of the current source to accumulate a capacitive charge redistribution of a predetermined amount of charge onto the integration capacitor. Thus, current is not maintained at the same level, rather, current spikes up at the outset to discharge the integration capacitor and exponentially reduces thereafter. While discharging at the outset is desirable because it avoids jitter sensitivity at integration stop time, power consumption is increased due to the greater current requirement. Accordingly, in the SC feedback approach, while the jitter sensitivity realized in the CT feedback approach is considerably mitigated due to smaller residue current at the end of the integration cycle (at t=T/2), power consumption is undesirably greater. The increase in power consumption is due to the burden the large current requirement of this approach places on the operational amplifier resulting in chip power penalties.
This is perhaps better understood with reference to FIG. 2. FIG. 2 shows a graph of current versus time and the integration of the IFB pursuant to a switched-capacitor (SC) Sigma-Delta feedback technique used a prior art ADC design. More specifically, the y-axis represents current through the integration capacitor and the x-axis represents time. At the outset, current is at its maximum value of Imax and reduces exponentially over time to finally reach zero or thereabout at T/2. Current being low at T/2 makes an SC feedback ADC suitable for low-jitter sensitivity and therefore for high resolution applications, however, power consumption suffers because of the increase needed to increase current at the outset. The feedback charge, QFB, is the integration of IFB over time.
In the SC feedback approach, jitter relaxation factor (D) is defined by the following equation:
                    D        =                              I            FB                                I            min                                              Eq        .                                  ⁢                  (          3          )                    
Where Imin is the value of current at t=T/2
D essentially represents a ratio of jitter sensitivity. Thus, jitter sensitivity is improved by D, in the SC feedback approach over the CT feedback approach. For a fair comparison of the SC and CT feedback techniques, the shaded areas in each of the FIGS. 1 and 2 should be substantially equal such that the integration capacitor in each case is discharged with the same amount of charge over the same integration time.
The total charge transferred during feedback (QFB) is determined by the following equation:
                                                                        Q                FB                            =                                                                    I                    FB                                    ·                                      T                    2                                                  =                                                                            ∫                      0                                              T                        /                        2                                                              ⁢                                                                  i                        ⁡                                                  (                          t                          )                                                                    ⁢                                                                                          ⁢                                              ⅆ                        t                                                                              =                                      τ                    ⁢                                                                                  ⁢                                          I                      max                                        ⁢                                          e                                                                        -                          t                                                /                        τ                                                                                                                                                  T            /            2                    0                =                              I            max                    ⁢                      τ            ⁡                          (                              1                -                                  e                                                                                    -                        T                                            /                      2                                        ⁢                    τ                                                              )                                                          Eq        .                                  ⁢                  (          4          )                    Where IFB is the equivalent constant feedback current, and τ is the time-constant of the discharge in the SC feedback case, ∫0T/2i(t)dt represents the integration of i over time and Imaxτ(1−e−T/2τ) represents the resulting exponential function.
Using Eq. (4), D can be represented by the following equation:
                    D        =                                            2              ⁢              τ                        T                    ⁢                      (                                          ⅇ                                                      T                    /                    2                                    ⁢                  τ                                            -              1                        )                                              Eq        .                                  ⁢                  (          5          )                    from which τ is obtained given the target D.Another useful parameter for comparison of the two different feedback cases is the operational amplifier current over-design factor (γ) which can be calculated as:
                    γ        =                                            I              max                                      I              FB                                =                                    T                              2                ⁢                τ                                      ·                          1                              (                                  1                  -                                      ⅇ                                                                                            -                          T                                                /                        2                                            ⁢                      τ                                                                      )                                                                        Eq        .                                  ⁢                  (          6          )                    Considering that
  τ  ⪡      T    2  this factor can be significant. In the event the operational amplifier cannot provide the maximum current Imax, it goes into a slewing mode creating nonlinearity, which is clearly undesirable as it results in degradation of the ADC performance. To provide the maximum current, Imax, power requirements increase, which is clearly a disadvantage.
Therefore, the need arises for a Sigma-Delta ADC having reduced jitter sensitivity while maintaining power consumption low.